FPGA Hardware Implementation and Experimental Validation of Efficient DOA Estimation Algorithms

About this project

• Centre for Smart Systems, AI and Cybersecurity (SSAICS)

The aim of this research project is to develop efficient algorithms for direction of arrival (DOA) estimation of both non-coherent and coherent sources and implement these algorithms on a field programmable gate array (FPGA) target for real-time experimental validation.

Estimation of direction of arrival angles of impinging radio frequency (RF) signals is an active and important research area owing to immense practical applications in both civilian and military fields such as sonar and radar for localisation of source, multiple-input multiple-out (MIMO) systems, and beam steering/forming smart antenna arrays in mobile communication. The practical significance of the DOA estimation problem can be established only through real-time testing on actual hardware for validation of the estimation methods. While there are several algorithms reported in the literature for DOA estimation, only a few of these are suitable for hardware implementation due to higher complexity, resource requirements, and computation time. Singular value decomposition (SVD) or eigen value decomposition (EVD) based algorithms such as ESPRIT and MUSIC, are not suitable for hardware implementation. In contrast, algorithms such as those based on LU factorization, Cholesky and LDL decomposition, and QR decomposition have lower computational complexity, which makes them suitable for real-time hardware implementation.

Wireless Communications & Signal Processing Research Lab, Prince Mohammad bin Fahd University, KSA.

• Hussain, Ahmed A., Tayem, Nizar, SOLIMAN, Abdel-Hamid and Radaydeh, Redha M. (2019) FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms. IEEE Access, 7. pp. 88845-88858. ISSN 2169-3536 )
• Hussain, Ahmed A., Tayem, Nizar, Butt, Muhammad Omair, SOLIMAN, Abdel-Hamid, Alhamed, Abdulrahman and Alshebeili, Saleh (2018) FPGA Hardware Implementation of DOA Estimation Algorithm Employing LU Decomposition. IEEE Access, 6. pp. 17666-17680. ISSN 2169-3536 )